As is known in the art, a silicon wafer having a {110} plane as the main surface allows the carrier mobility in a pMOS transistor to be higher than that of a wafer having a {100} plane as the main surface, thereby being used to provide high speed pMOS transistors.
From another aspect, an epitaxial wafer is used as a material for high performance devices because of having significantly few defects in an epitaxial layer. As such, an epitaxial wafer having a {110} plane as the main surface is expected to present remarkable properties as a material for high performance devices, such as an MPU.
However, an epitaxial wafer having a {110} plane as the main surface tends to generate a tarnish referred to as haze, and therefore it becomes difficult even to measure LPD (Light Point Defects) using a particle counter possibly with difficulty to perform quality assurance of wafers.
Against such difficulties, known in the art is to grow an epitaxial layer on a silicon single crystal substrate having an off-angle in the range of 0.5 degree to 3 degrees toward the <100> axis direction, thereby reducing the haze level (Patent Document 1).